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low-cost 3.3v zero delay buffe r cy2305 cy2309 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07140 rev. *d revised december 09, 2003 features ? 10-mhz to 100-/133-mhz operating range, compatible with cpu and pci bus frequencies ? zero input-output propagation delay ? multiple low-skew outputs ? output-output skew less than 250 ps ? device-device skew less than 700 ps ? one input drives five outputs (cy2305) ? one input drives nine outputs, grouped as 4 + 4 + 1 (cy2309) ? less than 200 ps cycle-cycle jitter, compatible with pentium ? -based systems ? test mode to bypass phase-locked loop (pll) (cy2309 only [see ?select input decoding? on page 2]) ? available in space-saving 16-pin 150-mil soic or 4.4-mm tssop packages (cy2309), and 8-pin, 150-mil soic package (cy2305) ? 3.3v operation ? industrial temperature available functional description the cy2309 is a low-cost 3.3v zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin soic or tssop package. the cy2305 is an 8-pin version of the cy2309. it accepts one reference input, and drives out five low-skew clocks. the -1h versions of each device operate at up to 100-/133-mhz frequencies, and have higher drive than the -1 devices. all parts have on-chip plls which lock to an input clock on the ref pin. the pll feedback is on-chip and is obtained from the clkout pad. the cy2309 has two banks of four outputs each, which can be controlled by the select inputs as shown in the ?select input decoding? table on page 2. if a ll output clocks are not required, bankb can be three-stated. the select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. the cy2305 and cy2309 plls enter a power-down mode when there are no rising edges on the ref input. in this state, the outputs are three-stated and the pll is turned off, resulting in less than 12.0 a of current draw for commercial temper- ature devices and 25.0 a for industrial temperature parts. the cy2309 pll shuts down in one additional case as shown in the table below. multiple cy2305 and cy2309 devices can accept the same input clock and distribute it. in this case, the skew between the outputs of two devices is guara nteed to be less than 700 ps. all outputs have less than 200 ps of cycle-cycle jitter. the input to output propagation delay on both devices is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250 ps. the cy2305/cy2309 is available in two/three different config- urations, as shown in the ordering information (page 10). the cy2305-1/cy2309-1 is the base part. the cy2305-1h/ cy2309-1h is the high-drive version of the -1, and its rise and fall times are much fa ster than the -1s. block diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ref clka1 clka2 v dd gnd clkb1 clkb2 s2 clkout clka4 clka3 v dd gnd clkb4 clkb3 s1 soic/tssop top view pin configuration 1 2 3 4 5 8 7 6 ref clk2 clk1 gnd v dd clkout clk4 clk3 soic top view pll mux select input ref s2 s1 clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 decoding clkout
cy2305 cy2309 document #: 38-07140 rev. *d page 2 of 13 notes: 1. weak pull-down. 2. weak pull-down on all outputs. 3. weak pull-ups on these inputs. 4. this output is driven and has an internal feedback for the pll. the load on this output can be adjusted to change the skew be tween the reference and output. pin description for cy2309 pin signal description 1ref [1] input reference frequency, 5v-tolerant input 2 clka1 [2] buffered clock output, bank a 3 clka2 [2] buffered clock output, bank a 4v dd 3.3v supply 5 gnd ground 6 clkb1 [2] buffered clock output, bank b 7 clkb2 [2] buffered clock output, bank b 8s2 [3] select input, bit 2 9s1 [3] select input, bit 1 10 clkb3 [2] buffered clock output, bank b 11 clkb4 [2] buffered clock output, bank b 12 gnd ground 13 v dd 3.3v supply 14 clka3 [2] buffered clock output, bank a 15 clka4 [2] buffered clock output, bank a 16 clkout [2] buffered output, internal feedback on this pin pin description for cy2305 pin signal description 1ref [1] input reference frequency, 5v-tolerant input 2clk2 [2] buffered clock output 3clk1 [2] buffered clock output 4 gnd ground 5clk3 [2] buffered clock output 6v dd 3.3v supply 7clk4 [2] buffered clock output 8 clkout [2] buffered clock output, internal feedback on this pin select input decoding for cy2309 s2 s1 clock a1?a4 clock b1?b4 clkout [4] output source pll shutdown 0 0 three-state three-state driven pll n 0 1 driven three-state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n
cy2305 cy2309 document #: 38-07140 rev. *d page 3 of 13 ref. input to clka/clkb delay vs. loading difference between clkout and clka/clkb pins zero delay and skew control all outputs should be uniformly loaded to achieve zero delay between the input and output. since the clkout pin is the internal feedback to the pll, its relative loading can adjust the input-output delay. this is shown in the above graph. for applications requiring zero input-output delay, all outputs, including clkout, must be equally loaded. even if clkout is not used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. if input to output delay adjustments are required, use the above graph to calculate loading differences between the clkout pin and other outputs. for zero output-output skew, be sure to load all outputs equally. for further information refer to the application note entitled ?cy2305 and cy2309 as pci and sdram buffers.?
cy2305 cy2309 document #: 38-07140 rev. *d page 4 of 13 absolute maximum conditions supply voltage to ground potential ............... ?0.5v to +7.0v dc input voltage (except ref) ............?0.5v to v dd + 0.5v dc input voltage ref......................................... ?0.5v to 7v storage temperature ................................. ?65 c to +150 c junction temperature ................................................. 150 c static discharge voltage (per mil-std-883, method 3015) .............. ............. > 2,000v operating conditions for cy2305sc-xx and cy2309sc-xx commercial temperature devices parameter description min. max. unit v dd supply voltage 3.0 3.6 v t a operating temperature (a mbient temperature) 0 70 c c l load capacitance, below 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 10 pf c in input capacitance 7 pf t pu power-up time for all v dd ?s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics for cy2305sc-xx and cy2309sc-xx commercial temperature devices parameter description test conditions min. max. unit v il input low voltage [5] 0.8 v v ih input high voltage [5] 2.0 v i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage [6] i ol = 8 ma (?1) i oh = 12 ma (?1h) 0.4 v v oh output high voltage [6] i oh = ?8 ma (?1) i ol = ?12 ma (?1h) 2.4 v i dd (pd mode) power down supply current ref = 0 mhz 12.0 a i dd supply current unloaded outputs at 66.67 mhz, sel inputs at v dd 32.0 ma switching characteristics for cy2305sc-1and cy2309sc-1 commercial temperature devices [7] parameter name test conditions min. typ. max. unit t1 output frequency 30-pf load 10-pf load 10 10 100 133.33 mhz mhz duty cycle [6] = t 2 t 1 measured at 1.4v, f out = 66.67 mhz 40.0 50.0 60.0 % t3 rise time [6] measured between 0.8v and 2.0v 2.50 ns t 4 fall time [6] measured between 0.8v and 2.0v 2.50 ns t 5 output to output skew [6] all outputs equally loaded 250 ps t 6a delay, ref rising edge to clkout rising edge [6] measured at v dd /2 0 350 ps t 6b delay, ref rising edge to clkout rising edge [6] measured at v dd /2. measured in pll bypass mode, cy2309 device only. 158.7ns t 7 device to device skew [6] measured at v dd /2 on the clkout pins of devices 0700ps t j cycle to cycle jitter [6] measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time [6] stable power supply, valid clock presented on ref pin 1.0 ms notes: 5. ref input has a threshold voltage of v dd /2. 6. parameter is guaranteed by design and charac terization. not 100% tested in production. 7. all parameters specified with loaded outputs.
cy2305 cy2309 document #: 38-07140 rev. *d page 5 of 13 switching characteristics for cy2305sc-1h and cy2309sc-1h commercial temperature devices [7] parameter name description min. typ. max. unit t1 output frequency 30-pf load 10-pf load 10 10 100 133.33 mhz mhz duty cycle [6] = t 2 t 1 measured at 1.4v, f out = 66.67 mhz 40.0 50.0 60.0 % duty cycle [6] = t 2 t 1 measured at 1.4v, f out < 50.0 mhz 45.0 50.0 55.0 % t3 rise time [6] measured between 0.8v and 2.0v 1.50 ns t 4 fall time [6] measured between 0.8v and 2.0v 1.50 ns t 5 output to output skew [6] all outputs equally loaded 250 ps t 6a delay, ref rising edge to clkout rising edge [6] measured at v dd /2 0 350 ps t 6b delay, ref rising edge to clkout rising edge [6] measured at v dd /2. measured in pll bypass mode, cy2309 device only. 158.7ns t 7 device to device skew [6] measured at v dd /2 on the clkout pins of devices 0700ps t 8 output slew rate [6] measured between 0.8v and 2.0v using test circuit #2 1v/ns t j cycle to cycle jitter [6] measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time [6] stable power supply, valid clock presented on ref pin 1.0 ms operating conditions for cy2305si-xx and cy2309si-xx industrial temperature devices parameter description min. max. unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) ?40 85 c c l load capacitance, below 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 10 pf c in input capacitance 7 pf electrical characteristics for cy2305si-xx and cy2309si-xx industrial temperature devices parameter description test conditions min. max. unit v il input low voltage [5] 0.8 v v ih input high voltage [5] 2.0 v i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage [6] i ol = 8 ma (?1) i oh =12 ma (?1h) 0.4 v v oh output high voltage [6] i oh = ?8 ma (?1) i ol = ?12 ma (?1h) 2.4 v i dd (pd mode) power-down supply current ref = 0 mhz 25.0 a i dd supply current unloaded outputs at 66.67 mhz, sel inputs at v dd 35.0 ma switching characteristics for cy2305si-1and cy2309si-1 industrial temperature devices [7] parameter name test conditions min. typ. max. unit t1 output frequency 30-pf load 10-pf load 10 10 100 133.33 mhz mhz duty cycle [6] = t 2 t 1 measured at 1.4v, f out = 66.67 mhz 40.0 50.0 60.0 % t3 rise time [6] measured between 0.8v and 2.0v 2.50 ns t 4 fall time [6] measured between 0.8v and 2.0v 2.50 ns
cy2305 cy2309 document #: 38-07140 rev. *d page 6 of 13 t 5 output to output skew [6] all outputs equally loaded 250 ps t 6a delay, ref rising edge to clkout rising edge [6] measured at v dd /2 0 350 ps t 6b delay, ref rising edge to clkout rising edge [6] measured at v dd /2. measured in pll bypass mode, cy2309 device only. 158.7ns t 7 device to device skew [6] measured at v dd /2 on the clkout pins of devices 0700ps t j cycle to cycle jitter [6] measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time [6] stable power supply, valid clock presented on ref pin 1.0 ms switching characteristics for cy2305si-1h and cy2309si-1h industrial temperature devices [7] parameter name descrip tion min. typ. max. unit t 1 output frequency 30-pf load 10-pf load 10 10 100 133.33 mhz mhz duty cycle [6] = t 2 t 1 measured at 1.4v, f out = 66.67 mhz 40.0 50.0 60.0 % duty cycle [6] = t 2 t 1 measured at 1.4v, f out < 50.0 mhz 45.0 50.0 55.0 % t 3 rise time [6] measured between 0.8v and 2.0v 1.50 ns t 4 fall time [6] measured between 0.8v and 2.0v 1.50 ns t 5 output to output skew [6] all outputs equally loaded 250 ps t 6a delay, ref rising edge to clkout rising edge [6] measured at v dd /2 0 350 ps t 6b delay, ref rising edge to clkout rising edge [6] measured at v dd /2. measured in pll bypass mode, cy2309 device only. 158.7ns t 7 device to device skew [6] measured at v dd /2 on the clkout pins of devices 0 700 ps t 8 output slew rate [6] measured between 0.8v and 2.0v using test circuit #2 1v/ns t j cycle to cycle jitter [6] measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time [6] stable power supply, valid clock presented on ref pin 1.0 ms switching characteristics for cy2305si-1and cy2309si-1 industrial temperature devices (continued) [7] parameter name test conditions min. typ. max. unit
cy2305 cy2309 document #: 38-07140 rev. *d page 7 of 13 switching waveforms duty cycle timing t 1 t 2 1.4v 1.4v 1.4v all outputs rise/fall time output t 3 3.3v 0v 0.8v 2.0v 2.0v 0.8v t 4 output-output skew 1.4v 1.4v t 5 output output input-output propagation delay v dd /2 t 6 input output v dd /2 v dd /2 v dd /2 t 7 clkout, device 1 clkout, device 2 device-device skew
cy2305 cy2309 document #: 38-07140 rev. *d page 8 of 13 typical duty cycle [8] and i dd trends [9] for cy2305-1 and cy2309-1 notes: 8. duty cycle is taken from typical chip measured at 1.4v. 9. i dd data is calculated from i dd = i core + ncvf, where i core is the unloaded current. (n = # of outputs; c = capacitance load per output (f); v = supply voltage (v); f = frequency (hz)). duty cycle vs vdd (for 30 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz dut y cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 30 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c duty cycle vs frequency (for 15 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c idd vs number of loaded outputs (for 30 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 0123456789 # of loaded outputs idd (ma) 33 mhz 66 mhz 100 mhz idd vs number of loaded outputs (for 15 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 0123456789 # of loaded outputs idd (ma) 33 mhz 66 mhz 100 mhz
cy2305 cy2309 document #: 38-07140 rev. *d page 9 of 13 typical duty cycle [8] and idd trends [9] for cy2305-1h and cy2309-1h duty cycle vs vdd (for 30 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz dut y cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 30 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c duty cycle vs frequency (for 15 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c idd vs number of loaded outputs (for 30 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 160 0123456789 # of loaded outputs idd (ma) 33 mhz 66 mhz 100 mhz idd vs number of loaded outputs (for 15 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 160 0123456789 # of loaded outputs idd (ma) 33 mhz 66 mhz 100 mhz
cy2305 cy2309 document #: 38-07140 rev. *d page 10 of 13 test circuits 0.1 f v dd 0.1 f v dd clk out c load outputs gnd gnd 0.1 f v dd 0.1 f v dd 10 pf outputs gnd gnd 1 k ? 1 k ? test circuit # 1 test circuit # 2 for parameter t 8 (output slew rate) on -1h devices ordering information ordering code package type operating range cy2305sc-1 8-pin 150-mil soic commercial cy2305sc-1t 8-pin 150-mil soic ? tape and reel commercial cy2305szc-1 8-pin 150-mil soic ? (lead-free) commercial cy2305szc-1t 8-pin 150-mil soic ? tape and reel ? (lead-free) commercial cy2305si-1 8-pin 150-mil soic industrial cy2305si-1t 8-pin 150-mil soic ? tape and reel industrial cy2305szi-1 8-pin 150-mil soic ? (lead-free) industrial cy2305szi-1t 8-pin 150-mil soic ? tape and reel ? (lead-free) industrial cy2305sc-1h 8-pin 150-mil soic commercial cy2305sc-1ht 8-pin 150-mil soic ? tape and reel commercial cy2305szc-1h 8-pin 150-mil soic ? (lead-free) commercial cy2305szc-1ht 8-pin 150-mil soic ? tape and reel ? (lead-free) commercial cy2305si-1h 8-pin 150-mil soic industrial cy2305si-1ht 8-pin 150-mil soic ? tape and reel industrial cy2305szi-1h 8-pin 150-mil soic ? (lead-free) industrial cy2305szi-1ht 8-pin 150-mil soic ? tape and reel ? (lead-free) industrial cy2305zc-1 8-pin 150-mil tssop commercial cy2305zc-1t 8-pin 150-mil tssop ? tape and reel commercial cy230s5zzc-1 8-pin 150-mil tssop ? (lead-free) commercial CY2305SZZC-1T 8-pin 150-mil tssop ? tape and reel - (lead-free) commercial cy2309sc-1 16-pin 150-mil soic commercial cy2309sc-1t 16-pin 150-mil soic ? tape and reel commercial cy2309szc-1 16-pin 150-mil soic ? (lead-free) commercial cy2309szc-1t 16-pin 150-mil soic ? tape and reel ? (lead-free) commercial cy2309si-1 16-pin 150-mil soic industrial cy2309si-1t 16-pin 150-mil soic ? tape and reel industrial cy2309szi-1 16-pin 150-mil soic ? (lead-free) industrial cy2309szi-1t 16-pin 150-mil soic ? tape and reel ? (lead-free) industrial cy2309sc-1h 16-pin 150-mil soic commercial
cy2305 cy2309 document #: 38-07140 rev. *d page 11 of 13 cy2309sc-1ht 16-pin 150-mil soic ? tape and reel commercial cy2309szc-1h 16-pin 150-mil soic ? (lead-free) commercial cy2309szc-1ht 16-pin 150-mil soic ? tape and reel ? (lead-free) commercial cy2309si-1h 16-pin 150-mil soic industrial cy2309si-1ht 16-pin 150-mil soic ? tape and reel industrial cy2309szi-1h 16-pin 150-mil soic ? (lead-free) industrial cy2309szi-1ht 16-pin 150-mil soic ? tape and reel ? (lead-free) industrial cy2309zc-1h 16-pin 4. 4-mm tssop commercial cy2309zc-1ht 16-pin 4.4-mm tssop ? tape and reel commercial cy2309zzc-1h 16-pin 4.4-mm tssop ? (lead-free) commercial cy2309zzc-1ht 16-pin 4.4-mm tssop ? tape and reel ? (lead-free) commercial cy2309zi-1h 16-pin 4. 4-mm tssop industrial cy2309zi-1ht 16-pin 4.4-mm tssop ? tape and reel industrial cy2309zzi-1h 16-pin 4.4-mm tssop ? (lead-free) industrial cy2309zzi-1ht 16-pin 4.4-mm tssop ? tape and reel ? (lead-free) industrial ordering information (continued) ordering code package type operating range package drawing and dimensions seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin1idisoptional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 8 lead (150 mil) soic - s08 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 8-lead (150-mil) soic s8 51-85066-*c
cy2305 cy2309 document #: 38-07140 rev. *d page 12 of 13 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. pentium is a registered trademark of inte l corporation. all product and company names mentioned in this document may be the trademarks of their respective holders. package drawing and dimensions (continued) pin 1 id 0~8 16 lead (150 mil) soic 1 8 916 seating plane 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.386[9.804] 0.393[9.982] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] dimensions in inches[mm] min. max. 0.016[0.406] 0.010[0.254] x 45 0.004[0.102] reference jedec ms-012 part # s16.15 standard pkg. sz16.15 lead free pkg. package weight 0.15gms 16-lead (150-mil) soic s16 51-85068-*b 4.90[0.193] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 16 pin 1 id 6.50[0.256] seating plane 1 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] bsc. 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] bsc 0.25[0.010] 0-8 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] plane gauge 16-lead thin shrunk small outline package (4.40 mm body) z16 51-85091-*a
cy2305 cy2309 document #: 38-07140 rev. *d page 13 of 13 document history page document title: cy2305/cy2309 low-cost 3.3v zero delay buffer document number: 38-07140 rev. ecn no. issue date orig. of change description of change ** 110249 10/19/01 szv change from spec number: 38-00530 to 38-07140 *a 111117 03/01/02 ckn added t6b row to the switching characteristics table; also ad ded the letter ?a? to the t6a row corrected the table title from cy2305sc-ih and cy2309sc-ih to cy2305si-ih and cy2309si-ih *b 117625 10/21/02 hwt added eight-pin tssop packages (cy2305zc-1 and cy2305zc-1t) to the ordering information table. added the tape and reel option to all the existing packages: cy2305sc-1t, cy2305si-1t, cy2305sc-1ht, cy2305si-1ht, cy2305zc-1t, cy2309sc-1t, cy2309si-1t, cy2309sc-1ht, cy2309si-1ht, cy2309zc-1ht, cy2309zi-1ht *c 121828 12/14/02 rbi power-up requirements added to operating conditions information *d 131503 11/25/03 rgl added lead-free for all the devices in the ordering information table

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